B&B Electronics RS-232 to Ethernet Converter ES1A Specifikace
Procházejte online nebo si stáhněte Specifikace pro Sítě B&B Electronics RS-232 to Ethernet Converter ES1A. B&B Electronics RS-232 to Ethernet Converter ES1A Specifications Uživatelská příručka
- Strana / 123
- Tabulka s obsahem
- KNIHY
- Features 1
- Applications 1
- Description 1
- Functional Block Diagram 1
- 2 Rev. 1.0 2
- TABLE OF CONTENTS 3
- 1. Electrical Specifications 4
- 8 Rev. 1.0 8
- Rev. 1.0 11 11
- 12 Rev. 1.0 12
- Rev. 1.0 13 13
- 14 Rev. 1.0 14
- Parameter 17
- Symbol Test Condition 17
- Max Unit 17
- Figure 9. SPI Timing Diagram 19
- Si3216(M) 20
- Rev. 1.0 21 21
- Rev. 1.0 23 23
- Component (s) Value Supplier 25
- , 1/10 W, ±5% 25
- 26 Rev. 1.0 26
- 2. Functional Description 27
- 2.1.2. Linefeed Architecture 28
- . The ProSLIC can 28
- Rev. 1.0 29 29
- Parameter Description/ 31
- Resolution Register 31
- Location* 31
- Closure Detection 32
- Switching 33
- 34 Rev. 1.0 34
- Figure 19. V 35
- in the Forward Active State 35
- 2.3. Tone Generation 36
- Tone Generator 1 38
- Tone Generator 2 38
- 2.4. Ringing Generation 39
- 2.4.2. Sinusoidal Ringing 40
- 2.4.3. Trapezoidal Ringing 40
- Location 40
- T=1/freq 41
- Figure 23. Ring Trip Detector 42
- 2.5. Audio Path 43
- 44 Rev. 1.0 44
- Rev. 1.0 45 45
- 2.7. Clock Generation 46
- 2.8. Interrupt Logic 46
- Rev. 1.0 47 47
- 48 Rev. 1.0 48
- 2.10. PCM Interface 49
- 50 Rev. 1.0 50
- Rev. 1.0 51 51
- 3. Control Registers 52
- Rev. 1.0 53 53
- 54 Rev. 1.0 54
- Rev. 1.0 55 55
- CALM1 CALM2 CALDAC CALADC 55
- 56 Rev. 1.0 56
- Rev. 1.0 57 57
- 58 Rev. 1.0 58
- Rev. 1.0 59 59
- 60 Rev. 1.0 60
- Rev. 1.0 61 61
- 62 Rev. 1.0 62
- Rev. 1.0 63 63
- 64 Rev. 1.0 64
- Rev. 1.0 65 65
- 66 Rev. 1.0 66
- Rev. 1.0 67 67
- 68 Rev. 1.0 68
- Rev. 1.0 69 69
- 70 Rev. 1.0 70
- Rev. 1.0 71 71
- 72 Rev. 1.0 72
- Rev. 1.0 73 73
- 74 Rev. 1.0 74
- Rev. 1.0 75 75
- 76 Rev. 1.0 76
- Rev. 1.0 77 77
- 78 Rev. 1.0 78
- Rev. 1.0 79 79
- 80 Rev. 1.0 80
- Rev. 1.0 81 81
- 82 Rev. 1.0 82
- Rev. 1.0 83 83
- 84 Rev. 1.0 84
- Rev. 1.0 85 85
- 86 Rev. 1.0 86
- Rev. 1.0 87 87
- 88 Rev. 1.0 88
- Rev. 1.0 89 89
- 90 Rev. 1.0 90
- Rev. 1.0 91 91
- 92 Rev. 1.0 92
- Rev. 1.0 93 93
- 94 Rev. 1.0 94
- Rev. 1.0 95 95
- 96 Rev. 1.0 96
- Rev. 1.0 97 97
- 98 Rev. 1.0 98
- Rev. 1.0 99 99
- 100 Rev. 1.0 100
- Rev. 1.0 101 101
- 102 Rev. 1.0 102
- Rev. 1.0 103 103
- 4. Indirect Registers 104
- Rev. 1.0 105 105
- 106 Rev. 1.0 106
- Rev. 1.0 107 107
- 108 Rev. 1.0 108
- Rev. 1.0 109 109
- 5. Pin Descriptions: Si3216 110
- Rev. 1.0 111 111
- 112 Rev. 1.0 112
- 6. Pin Descriptions: Si3201 113
- 7. Ordering Guides 114
- Rev. 1.0 115 115
- 116 Rev. 1.0 116
- Rev. 1.0 117 117
- 118 Rev. 1.0 118
- Rev. 1.0 119 119
- DOCUMENT CHANGE LIST 120
- Rev. 1.0 121 121
- CONTACT INFORMATION 122
- Mouser Electronics 123
Shrnutí obsahu
Rev. 1.0 12/08 Copyright © 2008 by Silicon Laboratories Si3216Not Recommended for New DesignsSi3216PROSLIC® PROGRAMMABLE WIDEBAND SLIC/CODEC WITH RING
Si321610 Rev. 1.0Not Recommended for New DesignsNoise Performance—Narrowband Audio ModeIdle Channel Noise4C-Message Weighted — — 15 dBrnCPsophometric
Si3216100 Rev. 1.0Not Recommended for New DesignsReset settings = 0001_0001Reset settings = 0000_1000Reset settings = 1000_1000Register 101. Common Mo
Si3216Rev. 1.0 101Not Recommended for New DesignsReset settings = 0000_0000Reset settings = 0000_0000Reset settings = 0000_1000Register 104. Analog DA
Si3216102 Rev. 1.0Not Recommended for New DesignsReset settings = 0000_0000Register 108. Enhancement EnableBitD7D6D5D4D3D2D1D0NameILIMEN FSKEN DCSU LC
Si3216Rev. 1.0 103Not Recommended for New Designs1DCFILDC-DC Converter Squelch.When enabled, this bit squelches noise in the audio band from the dc-dc
Si3216104 Rev. 1.0Not Recommended for New Designs4. Indirect RegistersIndirect registers are not directly mapped into memory but are accessible throu
Si3216Rev. 1.0 105Not Recommended for New Designs4.2. Digital Programmable Gain/AttenuationSee functional description sections of digital programmabl
Si3216106 Rev. 1.0Not Recommended for New DesignsTable 39. Digital Programmable Gain/Attenuation Indirect Registers Description Addr. Description Refe
Si3216Rev. 1.0 107Not Recommended for New Designs4.3. SLIC ControlSee descriptions of linefeed interface and power monitoring for guidelines on compu
Si3216108 Rev. 1.0Not Recommended for New Designs19 Power Alarm Threshold for Transistors Q1 and Q2. 3020Power Alarm Threshold for Transistors Q3 and
Si3216Rev. 1.0 109Not Recommended for New Designs4.4. FSK ControlFor detailed instructions on FSK signal generation, refer to “Application Note 32: F
Si3216Rev. 1.0 11Not Recommended for New DesignsFigure 3. Transmit and Receive Path SNDR—Narrowband ModeFigure 4. Overload Compression Performance1234
Si3216110 Rev. 1.0Not Recommended for New Designs5. Pin Descriptions: Si3216Pin # QFNPin # TSSOPName Description35 1 CS Chip Select.Active low. When
Si3216Rev. 1.0 111Not Recommended for New Designs5 9 SDCL DC Monitor.DC-DC converter monitor input used to detect overcurrent situations in the con-ve
Si3216112 Rev. 1.0Not Recommended for New Designs24 28 ITIPP Positive TIP Current Control.Analog current output driving Q1.25 29 ITIPNNegative TIP Cur
Si3216Rev. 1.0 113Not Recommended for New Designs6. Pin Descriptions: Si3201Pin # Name Input/OutputDescription1 TIP I/O TIP Output—Connect to the TIP
Si3216114 Rev. 1.0Not Recommended for New Designs7. Ordering GuidesTable 44. Device Ordering GuideDevice Description Wideband CodecDCFF Pin OutputPac
Si3216Rev. 1.0 115Not Recommended for New DesignsTable 45. Evaluation Kit Ordering GuideItem SupportedProSLICDescription LinefeedInterfaceSi3216PPQX-E
Si3216116 Rev. 1.0Not Recommended for New Designs8. Package Outline: 38-Pin QFNFigure 30 illustrates the package details for the Si321x. Table 46 lis
Si3216Rev. 1.0 117Not Recommended for New Designs9. Package Outline: 38-Pin TSSOPFigure 31 illustrates the package details for the Si321x. Table 47 l
Si3216118 Rev. 1.0Not Recommended for New Designs10. Package Outline: 16-Pin ESOICFigure 32 illustrates the package details for the Si3201. Table 48
Si3216Rev. 1.0 119Not Recommended for New Designs11. Silicon Labs Si3216 Support Documentation AN32: Si321x Frequency Shift Keying (FSK) Modulation
Si321612 Rev. 1.0Not Recommended for New DesignsFigure 5. Transmit Path Frequency Response—Narrowband ModeTypical ResponseTypical Response
Si3216120 Rev. 1.0Not Recommended for New DesignsDOCUMENT CHANGE LISTRevision 0.61 to Revision 0.9 Separated the Si3216/15 document into two data she
Si3216Rev. 1.0 121Not Recommended for New DesignsNOTES:
Si3216122 Rev. 1.0Not Recommended for New DesignsCONTACT INFORMATIONSilicon Laboratories Inc.400 West Cesar ChavezAustin, TX 78701Tel: 1+(512) 416-850
Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Silicon Laboratories: Si32
Si3216Rev. 1.0 13Not Recommended for New DesignsFigure 6. Receive Path Frequency Response—Narrowband Mode
Si321614 Rev. 1.0Not Recommended for New DesignsFigure 7. Transmit Group Delay Distortion—Narrowband ModeFigure 8. Receive Group Delay Distortion—Narr
Si3216Rev. 1.0 15Not Recommended for New DesignsTable 5. Linefeed Characteristics (VDDA, VDDD= 3.13 to 5.25 V, TA= 0 to 70 °C for K-Grade, –40 to 85 °
Si321616 Rev. 1.0Not Recommended for New DesignsTable 6. Monitor ADC Characteristics(VDDA, VDDD= 3.13 to 5.25 V, TA= 0 to 70 °C for K-Grade, –40 to 85
Si3216Rev. 1.0 17Not Recommended for New DesignsTable 9. Power Supply Characteristics (VDDA,VDDD= 3.13 to 5.25 V, TA= 0 to 70 °C for K-Grade, –40 to 8
Si321618 Rev. 1.0Not Recommended for New DesignsTable 10. Switching Characteristics—General InputsVDDA=VDDA= 3.13 to 5.25 V, TA= 0 to 70 °C for K-Grad
Si3216Rev. 1.0 19Not Recommended for New DesignsFigure 9. SPI Timing DiagramTable 12. Switching Characteristics—PCM Highway Serial InterfaceVD= 3.13 t
Si32162 Rev. 1.0Not Recommended for New Designs
Si321620 Rev. 1.0Not Recommended for New DesignsFigure 10. PCM Highway Interface Timing DiagramFigure 11. Si3216(M) Application Circuit Using Si3201PC
Si3216Rev. 1.0 21Not Recommended for New DesignsTable 13. Si3216(M) + Si3201 External Component ValuesComponent (s) Value SupplierC1,C2 10 µF, 6 V Cer
Si321622 Rev. 1.0Not Recommended for New DesignsFigure 12. Si3216(M) Typical Application Circuit Using Discrete Line Interface CircuitTable 14. Si3216
Si3216Rev. 1.0 23Not Recommended for New DesignsFigure 13. Si321x BJT/Inductor DC-DC Converter CircuitR1,R3 200 k, 1/10 W, 1%R2,R4,R5,R102,R104,R105
Si321624 Rev. 1.0Not Recommended for New DesignsFigure 14. Si321xM MOSFET/Transformer DC-DC Converter CircuitTable 15. Si321x BJT/Inductor DC-DC Conve
Si3216Rev. 1.0 25Not Recommended for New DesignsFigure 15. Si321x Optional Equivalent Q5, Q6 Bias CircuitTable 16. Si321xM MOSFET/Transformer DC-DC Co
Si321626 Rev. 1.0Not Recommended for New DesignsThe subcircuit above can be substituted into any of the ProSLIC solutions as an optional bias circuit
Si3216Rev. 1.0 27Not Recommended for New Designs2. Functional DescriptionThe ProSLIC is a single, low-voltage CMOS device thatprovides all SLIC, code
Si321628 Rev. 1.0Not Recommended for New Designs2.1.2. Linefeed ArchitectureThe ProSLIC is a low-voltage CMOS device that useseither an Si3201 linefee
Si3216Rev. 1.0 29Not Recommended for New DesignsFigure 17. Simplified ProSLIC Linefeed Architecture for TIP and RING Leads (One Shown)Table 22. ProSLI
Si3216Rev. 1.0 3Not Recommended for New DesignsTABLE OF CONTENTSSection Page1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . .
Si321630 Rev. 1.0Not Recommended for New Designs2.1.5. Power Monitoring and Line Fault DetectionIn addition to reporting voltages and currents, thePro
Si3216Rev. 1.0 31Not Recommended for New DesignsTable 24. Associated Power Monitoring and Power Fault RegistersParameter Description/ RangeResolution
Si321632 Rev. 1.0Not Recommended for New DesignsFigure 18. Loop Closure Detection2.1.6. Loop Closure DetectionA loop closure event signals that the te
Si3216Rev. 1.0 33Not Recommended for New Designs2.1.9. Linefeed CalibrationAn internal calibration algorithm corrects for internal andexternal compone
Si321634 Rev. 1.0Not Recommended for New Designspower supply (number of REN supported).For this solution, an n-channel power MOSFET (M1)switches the c
Si3216Rev. 1.0 35Not Recommended for New DesignsFigure 19. VTIP, VRING, and VBAT in the Forward Active StateTable 27. Associated Relevant DC-DC Conver
Si321636 Rev. 1.0Not Recommended for New Designs2.2.5. DC-DC Converter EnhancementsThe ProSLIC supports two selectable enhancements tothe dc-dc conver
Si3216Rev. 1.0 37Not Recommended for New Designs2.3.2. Oscillator Frequency and AmplitudeEach of the two-tone generators contains a two-poleresonant o
Si321638 Rev. 1.0Not Recommended for New DesignsFigure 21. Tone Generator Timing DiagramTable 28. Associated Tone Generator RegistersTone Generator 1P
Si3216Rev. 1.0 39Not Recommended for New Designs2.3.4. Enhanced FSK Waveform GenerationEnhanced FSK generation capabilities can be enabledby setting F
Si32164 Rev. 1.0Not Recommended for New Designs1. Electrical SpecificationsTable 1. Absolute Maximum Ratings and Thermal Information1Parameter Symbol
Si321640 Rev. 1.0Not Recommended for New Designs2.4.2. Sinusoidal RingingTo configure the ProSLIC for sinusoidal ringing, thefrequency and amplitude a
Si3216Rev. 1.0 41Not Recommended for New DesignsFigure 22. Trapezoidal Ringing WaveformTo configure the ProSLIC for trapezoidal ringing, theuser shoul
Si321642 Rev. 1.0Not Recommended for New DesignsThe ProSLIC is designed to create a fully-balancedringing waveform, meaning that the TIP and RINGcommo
Si3216Rev. 1.0 43Not Recommended for New Designs2.5. Audio PathUnlike traditional SLICs, the codec function is integratedinto the ProSLIC. The 16-bit
Si321644 Rev. 1.0Not Recommended for New Designs+MuteATX+InterpolationFilterMuteDACGSerialInputDecimationFilterRHPFTHPFSerialOutputDigitalRXDigitalTXD
Si3216Rev. 1.0 45Not Recommended for New Designs2.5.2. Receive PathIn the receive path, digital voice is expanded from µ/A-law if enabled. DACG is the
Si321646 Rev. 1.0Not Recommended for New Designssubscriber loop via the ITIPP and IRINGP pins throughan off-chip current buffer (IBUF), which is imple
Si3216Rev. 1.0 47Not Recommended for New Designsthe command/address byte indicate the address of theregister to be accessed. The second byte of the pa
Si321648 Rev. 1.0Not Recommended for New DesignsFigure 28. SPI Daisy Chain Mode CPUSDOCSSDICSSDISDITHRUSDOCSSDISDITHRUSDOC7 C6 C5 C4 C3 C2 C1 C0 R
Si3216Rev. 1.0 49Not Recommended for New Designs2.10. PCM InterfaceThe ProSLIC contains a flexible programmable interfacefor the transmission and rec
Si3216Rev. 1.0 5Not Recommended for New DesignsTable 2. Recommended Operating ConditionsParameter Symbol Test Condition Min* Typ Max* UnitAmbient Temp
Si321650 Rev. 1.0Not Recommended for New DesignsTable 32. µ-Law Encode-Decode Characteristics1,2Segment Number#Intervals X Interval Size Value at Segm
Si3216Rev. 1.0 51Not Recommended for New DesignsTable 33. A-Law Encode-Decode Characteristics1,2Segment Number#intervals X interval size Value at segm
Si321652 Rev. 1.0Not Recommended for New Designs3. Control RegistersNote: Any register not listed here is reserved and must not be written.Table 34.
Si3216Rev. 1.0 53Not Recommended for New Designs31 Indirect Address Status IASOscillators32 Oscillator 1 Control OSS1 REL OZ1 O1TAE O1TIE O1E O1SO[1:0
Si321654 Rev. 1.0Not Recommended for New Designs68 Loop Closure/Ring Trip Detect StatusDBIRAW RTP LCR69 Loop Closure Debounce IntervalLCDI[6:0]70 Ring
Si3216Rev. 1.0 55Not Recommended for New Designs96 Calibration Control/Status Register 1CAL CALSP CALR CALT CALD CALC CALIL97 Calibration Control/Stat
Si321656 Rev. 1.0Not Recommended for New DesignsReset settings = 00xx_xxxxRegister 0. SPI Mode SelectBitD7D6D5D4D3D2D1D0NameSPIDC SPIM PNI[1:0] RNI[3
Si3216Rev. 1.0 57Not Recommended for New DesignsReset settings = 1000_1000Register 1. PCM Mode SelectBitD7D6D5D4D3D2D1D0NamePNI2 WBE PCME PCMF[1:0] P
Si321658 Rev. 1.0Not Recommended for New DesignsReset settings = 0000_0000Reset settings = 0000_0000Reset settings = 0000_0000Register 2. PCM Transmi
Si3216Rev. 1.0 59Not Recommended for New DesignsReset settings = 0000_0000Reset settings = 0xx0_0000Register 5. PCM Receive Start Count—High ByteBitD7
Si32166 Rev. 1.0Not Recommended for New DesignsTable 3. AC Characteristics—Wideband Audio Mode: Si3216(VDDA, VDDD= 3.13 to 5.25 V, TA= 0 to 70 °C for
Si321660 Rev. 1.0Not Recommended for New DesignsReset settings = 0000_0010Register 8. Audio Path Loopback ControlBitD7D6D5D4D3D2D1D0NameALM2 DLM ALM1T
Si3216Rev. 1.0 61Not Recommended for New DesignsReset settings = 0000_0000Register 9. Audio Gain ControlBitD7D6D5D4D3D2D1D0NameRXHP TXHP TXM RXM ATX[1
Si321662 Rev. 1.0Not Recommended for New DesignsReset settings = 0000_1000Register 10. Two-Wire Impedance Synthesis ControlBitD7D6D5D4D3D2D1D0NameCLC[
Si3216Rev. 1.0 63Not Recommended for New DesignsReset settings = 0011_0011Register 11. Hybrid ControlBitD7D6D5D4D3D2D1D0NameHYBP[2:0] HYBA[2:0]Type R/
Si321664 Rev. 1.0Not Recommended for New DesignsReset settings = 0001_0000Register 14. Powerdown Control 1BitD7D6D5D4D3D2D1D0NameDCOF PFR BIASOF SLICO
Si3216Rev. 1.0 65Not Recommended for New DesignsReset settings = 0000_0000Register 15. Powerdown Control 2BitD7D6D5D4D3D2D1D0NameADCM ADCON DACM DACON
Si321666 Rev. 1.0Not Recommended for New DesignsReset settings = 0000_0000Register 18. Interrupt Status 1BitD7D6D5D4D3D2D1D0NameRGIP RGAP O2IP O2AP O1
Si3216Rev. 1.0 67Not Recommended for New DesignsReset settings = 0000_0000Register 19. Interrupt Status 2BitD7D6D5D4D3D2D1D0NameQ6AP Q5AP Q4AP Q3AP Q2
Si321668 Rev. 1.0Not Recommended for New DesignsReset settings = 0000_0000Register 20. Interrupt Status 3BitD7D6D5D4D3D2D1D0NameINDPType R/WBit Name F
Si3216Rev. 1.0 69Not Recommended for New DesignsReset settings = 0000_0000Register 21. Interrupt Enable 1BitD7D6D5D4D3D2D1D0NameRGIE RGAE O2IE O2AE O1
Si3216Rev. 1.0 7Not Recommended for New DesignsNoise Performance—Wideband Audio ModeIdle Channel Noise37 kHz flat — — 23 dBrnPSRR from VDDARX and TX,
Si321670 Rev. 1.0Not Recommended for New DesignsReset settings = 0000_0000Register 22. Interrupt Enable 2BitD7D6D5D4D3D2D1D0NameQ6AE Q5AE Q4AE Q3AE Q2
Si3216Rev. 1.0 71Not Recommended for New DesignsReset settings = 0000_0000Register 23. Interrupt Enable 3BitD7D6D5D4D3D2D1D0NameINDEType R/WBit Name F
Si321672 Rev. 1.0Not Recommended for New DesignsReset settings = 0000_0000Reset settings = 0000_0000Register 28. Indirect Data Access—Low ByteBitD7D6D
Si3216Rev. 1.0 73Not Recommended for New DesignsReset settings = xxxx_xxxxReset settings = 0000_0000Register 30. Indirect AddressBitD7D6D5D4D3D2D1D0Na
Si321674 Rev. 1.0Not Recommended for New DesignsReset settings = 0000_0000Register 32. Oscillator 1 ControlBitD7D6D5D4D3D2D1D0NameOSS1 REL OZ1 O1TAE O
Si3216Rev. 1.0 75Not Recommended for New DesignsReset settings = 0000_0000Register 33. Oscillator 2 ControlBitD7D6D5D4D3D2D1D0NameOSS2 OZ2 O2TAE O2TIE
Si321676 Rev. 1.0Not Recommended for New DesignsReset settings = 0000_0000Register 34. Ringing Oscillator ControlBitD7D6D5D4D3D2D1D0NameRSS RDAC RTAE
Si3216Rev. 1.0 77Not Recommended for New DesignsReset settings = 0000_0000Reset settings = 0000_0000Reset settings = 0000_0000Register 36. Oscillator
Si321678 Rev. 1.0Not Recommended for New DesignsReset settings = 0000_0000Reset settings = 0000_0000Reset settings = 0000_0000Register 39. Oscillator
Si3216Rev. 1.0 79Not Recommended for New DesignsReset settings = 0000_0000Reset settings = 0000_0000Reset settings = 0000_0000Register 42. Oscillator
Si32168 Rev. 1.0Not Recommended for New DesignsFigure 1. Transmit and Receive Path Attenuation Distortion—Wideband ModeFigure 2. Transmit and Receive
Si321680 Rev. 1.0Not Recommended for New DesignsReset settings = 0000_0000Reset settings = 0000_0000Reset settings = 0000_0000Register 49. Ringing Osc
Si3216Rev. 1.0 81Not Recommended for New DesignsReset settings = 0000_0000Reset settings = 0101_0100Register 52. FSK DataBitD7D6D5D4D3D2D1D0NameFSKDAT
Si321682 Rev. 1.0Not Recommended for New DesignsReset settings = 0000_0000Register 64. Linefeed ControlBitD7D6D5D4D3D2D1D0NameLFS[2:0] LF[2:0]Type RR/
Si3216Rev. 1.0 83Not Recommended for New DesignsReset settings = 0110_0001Register 65. External Bipolar Transistor ControlBitD7D6D5D4D3D2D1D0NameSQH C
Si321684 Rev. 1.0Not Recommended for New DesignsReset settings = 0000_0011Register 66. Battery Feed ControlBitD7D6D5D4D3D2D1D0NameVOV FVBAT TRACKType
Si3216Rev. 1.0 85Not Recommended for New DesignsReset settings = 0001_1111Register 67. Automatic/Manual ControlBitD7D6D5D4D3D2D1D0NameMNCM MNDIF SPDS
Si321686 Rev. 1.0Not Recommended for New DesignsReset settings = 0000_0000Reset settings = 0000_1010Register 68. Loop Closure/Ring Trip Detect StatusB
Si3216Rev. 1.0 87Not Recommended for New DesignsReset settings = 0000_1010Reset settings = 0000_0000Register 70. Ring Trip Detect Debounce IntervalBit
Si321688 Rev. 1.0Not Recommended for New DesignsReset settings = 0010_0000Reset settings = 0000_0010Register 72. On-Hook Line VoltageBitD7D6D5D4D3D2D1
Si3216Rev. 1.0 89Not Recommended for New DesignsReset settings = 0011_0010Reset settings = 0001_0000Register 74. High Battery VoltageBitD7D6D5D4D3D2D1
Si3216Rev. 1.0 9Not Recommended for New DesignsTable 4. AC Characteristics—Narrowband Audio Mode(VDDA, VDDD= 3.13 to 5.25 V, TA= 0 to 70 °C for K-Grad
Si321690 Rev. 1.0Not Recommended for New DesignsReset settings = 0000_0000Reset settings = 0000_0000Register 76. Power Monitor PointerBitD7D6D5D4D3D2D
Si3216Rev. 1.0 91Not Recommended for New DesignsReset settings = 0000_0000Reset settings = 0000_0000Register 78. Loop Voltage SenseBitD7D6D5D4D3D2D1D0
Si321692 Rev. 1.0Not Recommended for New DesignsReset settings = 0000_0000Reset settings = 0000_0000Reset settings = 0000_0000Register 80. TIP Voltage
Si3216Rev. 1.0 93Not Recommended for New DesignsReset settings = 0000_0000Reset settings = xxxx_xxxxReset settings = xxxx_xxxxRegister 83. Battery Vol
Si321694 Rev. 1.0Not Recommended for New DesignsReset settings = xxxx_xxxxReset settings = xxxx_xxxxReset settings = xxxx_xxxxRegister 86. Transistor
Si3216Rev. 1.0 95Not Recommended for New DesignsReset settings = xxxx_xxxxReset settings = 1111_1111Register 89. Transistor 6 Current SenseBitD7D6D5D4
Si321696 Rev. 1.0Not Recommended for New DesignsReset settings = 0001_0100 (Si3216)Reset settings = 0011_0100 (Si3216M)Reset settings = 0000_0000Regis
Si3216Rev. 1.0 97Not Recommended for New DesignsReset settings = 0001_1111Register 96. Calibration Control/Status Register 1BitD7D6D5D4D3D2D1D0NameCAL
Si321698 Rev. 1.0Not Recommended for New DesignsReset settings = 0001_1110Register 97. Calibration Control/Status Register 2BitD7D6D5D4D3D2D1D0NameCAL
Si3216Rev. 1.0 99Not Recommended for New DesignsReset settings = 0001_0000Reset settings = 0001_0000Reset settings = 0001_0001Register 98. RING Gain M
Další dokumenty pro Sítě B&B Electronics RS-232 to Ethernet Converter ES1A
Související produkty a manuály pro Sítě B&B Electronics RS-232 to Ethernet Converter ES1A
(70 stránky)
(15 stránky)
(25 stránky)
(58 stránky)
(79 stránky)
(60 stránky)
(49 stránky)
(84 stránky)
(10 stránky)
(43 stránky)
© 2020, manymanuals.cz. Všechna práva vyhrazena. | 0.052 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Komentáře k této Příručce