B&B Electronics PC Watchdog Timer Card ATRWDT Uživatelský manuál stáhnout pdf (Strana 25)

P104-WDG-CSM User Manual

OUT: Current state of counter output pin.

NC: Null count. this indicates when the last count loaded into the counter register has

actually been loaded into the counter itself. The exact time of load depends on the

configuration selected. Until the count is loaded into the counter itself, it cannot be read.

RW0 and RW1: Read/Write command.

M0-M2: Counter mode.

BCD: BCD=0 sets binary mode, otherwise counter is in BCD mode.

If STA and CNT bits in the readback command byte are set low and the RW1 and RW0 bits

have both been previously set high in the counter control register (thus selecting two-byte

reads), then reading a counter address location will yield:

1st Read: Status byte

2nd Read: Low byte of latched data

3rd Read: High byte of latched data.

After any latching operation of a counter, the contents of its hold register must be read before

any subsequent latches of that counter will have any effect. If a status latch command is

issued before the hold register is read, then the first read will read the status, not the latched

value.

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B&B Electronics PC Watchdog Timer Card ATRWDT Uživatelský manuál Strana 25