P104-WDG-CSM User Manual
15
82c54 Registers (BASE +0 thru +3)
See Appendix A of this manual.
Status Register (BASE+4)
Bit assignments of the Status Register are as follows:
BD0 Watchdog counter refresh reminder (active low)
BD1 Temperature good (active low)
BD2 Reset Isolated Input #2 status
BD3 Isolated Input #1 status
BD4 Fan good
BD5 Power Supply overvoltage (active low)
BD6 Power Supply undervoltage (active low)
BD7 IRQ generated (active high)
Interrupts will be enabled AFTER this register is READ. Note that if interrupts are disabled
before accessing this register, bit 7 of the returned value will be zero (low). If a circuit needs
service then the second time this register is READ bit 7 will be high. Interrupts are disabled at
power-up to prevent an interrupt during boot-up.
Computer Temperature Monitor (BASE+5)
Available on both “CSM and CSMA” models, the temperature inside the enclosure can be
read using an 8-bit register at BASE+5. To convert the byte read into temperature in
Fahrenheit, multiply the value read by 11/15 and then add 7.
A/DC Channel #1 (BASE+6)
Read 8-bit general purpose analog input (0-5V).
Watchdog Programming Options (BASE+7)
Programming the card is straightforward. Counters 0 and 1 of the type 8254 counter/timer are
concatenated and operate as a 32-bit down counter to provide the time delay before a timeout
occurs. A special register provides enable and disable functions for the counters and, thus,
the watchdog itself. Writing any value to the register located at base address +7 enables the
counters to count. Reading the register disables the counters and stops the watchdog.
Status Register Image (BASE+8)
Read base +8 to get the Status value without changing the Interrupt enabled/disabled state.
Disable Interrupts (BASE+9)
Read base address +9 to disable interrupts. If interrupts were enabled and a circuit was
requesting attention then bit 7 will be high. A second reading of this register will have bit 7
LOW.
A/DC Channel #2 (BASE+A)
Read 8-bit general purpose analog input (0-5V).
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